INTRIQ Seminar

A pathway for quantum computing in silicon

Jonathan Baugh

Institute for Quantum Computing
University of Waterloo

We have recently proposed a network-of-nodes architecture [1] for assembling a large-scale quantum information processor with electron spin qubits. This architecture addresses some of the practical challenges to scaling up, and motivates experimental research on simplified device geometries and spin-coherent electron shuttling. The talk will describe how the surface code for quantum error correction is mapped to this network, and how fault tolerance thresholds are estimated. Simulation results on spin shuttling and experimental results on MOS quantum dots will be presented, along with perspectives on some of the key challenges to scaling.

[1] B. Buonacorsi et al, Quantum Science and Technology 4, 025003 (2019).